1. Field of the Invention
The present invention relates generally to the design of electronic circuits, and more specifically to a method and apparatus to increase the range of common mode voltages a circuit can operate with, while processing input signals.
2. Related Art
An electronic circuit generally accepts one or more input signals, processes them in some manner and correspondingly provides one or more output signals. For example, an amplifier may accept an audio signal and provide an amplified version of the audio signal as an output.
All signals in a circuit are referenced to one or more reference terminals, usually a ground terminal. For example, an input signal may be applied between an input terminal and a terminal connected to a ground reference point(circuit ground). The corresponding output signal may be provided between an output terminal and the circuit ground. An input (or output) signal which is referenced to a common ground terminal of a circuit(circuit ground) is called a single-ended signal.
In some environments, it is desirable to provide input signals to a circuit on terminals none of which are connected directly to circuit ground. This may be done in environments where the input signals are weak (low signal strength) and the entire circuit is operating in the presence of considerable noise (unwanted interfering signals).
For example, in a data-acquisition and control system, input signals may come from transducers located some distance from the main processing circuitry. Signals from transducers are typically low strength (weak) signals and may have to travel appreciable distances (through wires) before they can be processed.
In such environments, an input signal to a circuit is applied between two terminals (called differential input terminals), and the input signal is called a differential input signal and is not referenced to circuit ground. For example, a differential amplifier such as an operation amplifier (OPAMP) has two input terminals, inverting and non-inverting, between which a differential input signal may be applied. The OPAMP may amplify such a differential input signal and provide an output signal which may be single-ended or differential.
A differential signal (as in above environments) is characterized by a strength which equals the difference between the voltage(or current) values present on the two input terminals. The input signal may also contain a signal component which is common to both the input terminals. Such a common component is referred to as a common mode signal and is defined as the average of the voltage (or current) values present on the two input terminals.
A circuit such as an operational amplifier noted above may also receive single-ended input signals. In such a case, one input terminal of the circuit is connected to the single-ended signal and a second terminal of the circuit is connected to a reference voltage. Such a circuit is also characterized by a common-mode voltage (strength) at the two input terminals.
There has been a general constraint that the common-mode signal input (or equivalently the common-mode voltage/strength at the input terminals) to circuits (such as operational amplifiers) be limited to a certain range in order to ensure proper circuit functioning. For example, in the case of operational amplifiers there is a maximum specified common-mode voltage range for an input signal.
It is also desirable that the input common-mode range of a circuit (such as a differential amplifier) with differential (or single-ended) inputs be as high as possible, thus allowing a wide range of input signals to be processed. This is further described below with respect to an environment containing a sample-and-hold stage in an analog-to-digital converter (ADC).
FIG. 1 is a block diagram of a pipeline ADC in one embodiment illustrating the need to increase the input common mode range of an input (sample-and-hold circuitry) circuit. ADC 100 is shown containing sample and hold amplifier (SHA) 110, stages 120-1 through 120-S, digital error correction block 130 and reference buffer 150. Each block is described below in further detail.
Reference buffer 150 generates a reference voltage (Vref) on path 152 typically from a constant DC voltage (Vdc, e.g., bandgap reference voltage, well known in the relevant arts). Reference voltage (Vref) is used in various stages of the ADC for comparison against the signals at the respective inputs (on paths 111-1 through 111-S).
Digital error correction block 130 receives sub-codes from various stages (on paths 123-1 through 123-S respectively), and generates a digital code corresponding to the sample received on path 101. Various error correction approaches, well known in the relevant arts, may be used to correct any errors in the received sub-codes. The generated digital code is provided on path 139 as a final digital code corresponding to the voltage of a sample on the input analog signal at a particular time instant.
Each stage 120-1 through 120-S generates a sub-code (based on the reference signal Vref received on path 152) corresponding to a voltage level of an analog signal received as an input, and an amplified residue signal as an input to a (any) next stage. For example, stage 120-1 converts a voltage level on path 111-1 to generate a sub-code on path 123-1, and the amplified residue signal generated on path 111-2 is provided as an input to stage 120-2.
A common reference signal Vref is provided to stages 120-1 through 120-S. Each of stages 120-1 through 120-S may further contain various(logical) components such as a flash ADC, digital-to-analog converter (DAC), subtractor and gain amplifier as is well known in the relevant arts.
SHA 110 samples the input analog signal received on path 101 and holds the voltage level of the sample on path 111-1 for further processing. Path 101 contains two terminals between which an input differential signal may be applied. As noted above, the differential signals contain a common mode signal. The need for a high range of common mode signal can be better appreciated by examining the details and operation of SHA 110 in one embodiment.
Various terms used in the description and subsequent analysis are first listed below:
INP is the voltage at terminal 290-1
INM is the voltage at terminal 290-2
OUTP is the voltage at terminal 270-1
OUTM is the voltage at terminal 270-2
INP−INM represents the strength of the differential input signal received across terminals 290-1 and 290-2 and is the signal of interest.
OUTP−OUTM represents the strength of differential output signal provided across terminals 270-1 and 270-2 and is the signal of interest
INPCM=(INP+INM)/2), wherein INPCM is the common-mode voltage present in input signal applied across terminals 290-1 and 290-2
OUTCM is the common-mode voltage present at output terminals 270-1 and 270-2 due to application of an internally generated (in differential amplifier 260) reference voltage (REFCM). (In the interest of clarity, it is assumed for the purpose of this description that the output common mode feedback loop (noted earlier) is perfect, and that OUTCM gets set exactly to REFCM. For this reason, OUTCM and REFCM may be used interchangeably to refer to the same voltage.
REFCM(equal to (REFP+REFM)/2) is a common-mode voltage generated by internal (to differential amplifier 260) reference voltages REFP and REFM.
INCM is the common-mode voltage applied at input terminals (280-1 and 280-2) of differential amplifier 260 due to application of a reference voltage INCM and represents the value of the common-mode voltage that must be maintained at input terminals 280-1 and 280-2.
AMPINP is the voltage at 280-1 in the hold phase and AMPINM is the voltage at 280-2 in the hold phase. AMPCM is the effective common-mode voltage present at terminals 280-1 and 280-2 due to all sources of common-mode voltage (namely, INPCM, OUTCM and INCM) during the hold phase (between durations 391-392 of FIG. 3). AMPCM is equal to (AMPINP+AMPINM)/2.
Gd is the overall gain of the SHA 110 and is equal to (OUTP−OUTM)/(INP−INM).
Ao is the open loop differential gain of the differential amplifier 260 which is equal to (voltage at terminal 270-2−voltage at terminal 270-1)/(AMPINP−AMPINM)
FIG. 2 shows the internal details of SHA 110 in one embodiment. SHA 110 receives a differential input signal (that needs to be sampled at held for analog-to-digital conversion and further processing) across terminals 290-1 and 290-2 (logically contained in path 101), and is shown containing elements differential amplifier 260, switches 250-1, 250-2, 220-1, 220-2, 240-1 and 240-2, and capacitors 210-1, 210-2, 230-1 and 230-2. Each element is described below in further detail.
Differential amplifier 260 amplifies the difference of the voltages present across terminals 280-1 and 280-2, and provides an amplified output voltage across terminals 270-1 and 270-2. The differential output is connected (fed-back) to the terminals 280-1 and 280-2 through capacitors 210-1 and 210-2. Due to the feedback connection, differential amplifier 260 provides a differential output signal (across terminals 270-1 and 270-2), which is equal to the differential input signal. The differential output signal is used in subsequent stages (illustrated in FIG. 1) for further processing.
To ensure proper operation of differential amplifier 260, terminals 280-1 and 280-2 generally need to be maintained at a constant pre-determined bias potential. To achieve this, reference voltages are applied to terminals 280-1 and 280-2 through switches 220-1 and 220-2. Such an application causes a desired common-mode voltage to be maintained at terminals 280-1 and 280-2. The reference voltages noted above are selected such that the virtual ground nodes of the amplifier (280-1 and 280-2) are at an optimum value to ensure reliable operation. That is, the transistors contained in differential amplifier 260 are biased such that the amplifier operates with the desired high DC gain.
Similarly, the output terminals 270-1 and 270-2 of differential amplifier 260 may also need to be maintained at a constant pre-determined bias potential to ensure proper operation of any differential circuitry whose inputs may be connected to output terminals 270-1 and 270-2 of differential amplifier 260. This is achieved by a common mode feedback loop (not shown) which forces the output common mode which is equal to ((voltage at terminal 270-1+voltage at terminal 270-2)/2) to an internally generated voltage REFCM(equal to (REFP+REFM)/2).
Capacitors 230-1 and 230-2 represent parasitic capacitances at terminals 280-1 and 280-2 respectively. Switches 250-1, 250-2, 240-1 and 240-2, and capacitors 210-1, 210-2 operate to sample an input signal applied across input terminals 290-1 and 290-2 and hold the sampled value for amplification by differential amplifier 260. The manner in which this sample-and-hold operates is described below with reference to FIG. 3, which contains a timing diagram used to illustrate the sample and hold phases of SHA 110.
SHA 110 operates using two phases, shown in FIG. 3 as sampling phase 370 and hold phase 390. In the first phase (sampling phase 370) switches 250-1, 250-2, 220-1 and 220-2 are closed at time points 371 and the remaining switches 240-1 and 240-2 are kept open. As a result, capacitors 210-1 and 210-2 are ideally charged (in duration between 371-372) to the voltage of input signal present across terminals 290-1 and 290-2 by time point 372, and, 230-1 and 230-2 are ideally charged (in duration between 371-372) to the voltage (INCM) present at terminals 225-1 and 225-2.
In the second phase (between durations 391-392), feedback switches 240-1 and 240-2 are closed and switches 250-1, 250-2, 220-1 and 220-2 are kept open. This causes the output (across terminals 270-1 and 270-2) of amplifier 260 to take on a magnitude that is a function of the input signal (received on terminals 290-1 and 290-2), and the reference voltages INCM (applied on terminals 225-1 and 225-2) and OUTCM (applied on terminals 225-1 and 225-2). Expressions for the magnitude of the output voltage and the magnitudes of the differential and common-mode voltages at various nodes of SHA 110 are derived below.
As differential amplifier 260 is connected as a unity gain amplifier, the differential output voltage (OUTP−OUTM) is equal in magnitude to the differential input voltage (INP−INM), which is as required.
The common-mode voltages at various nodes are derived below. For the sake of clarity, voltages at various nodes are derived assuming only common-mode voltages are present.
During the sample phase switches 250-1, 250-2, 220-1 and 220-2 are closed, while switches 240-1 and 240-2 are open.
Therefore charge at each of input terminals 280-1 and 280-2 at the end of the sample phase is given by:Q=Cs(INCM−INPCM)+Cp(INCM)  Equation (1)
During the hold phase, switches 240-1 and 240-2 are closed and switches 250-1, 250-2, 220-1 and 220-2 are open.
Therefore charge at each of input terminals 280-1 and 280-2 at the end of the hold phase is given by:Q=Cs(AMPCM−OUTCM)+Cp(AMPCM)  Equation (2)
Input terminals 280-1 and 280-2 are high impedance nodes and hence charge at these nodes must be conserved. Therefore, equating equations 1 and 2 gives
                    AMPCM        =                  INCM          +                                    (                                                OUTCM                  -                  INPCM                                                                      C                    s                                    +                                      C                    p                                                              )                        ⁢                          C              s                                                          Equation        ⁢                                  ⁢                  (          3          )                    
Thus, it may be seen that due to the feedback of the output signal and application of an input signal, AMPCM has a value different from the required value of INCM, the difference being equal to (OUTCM−INPCM)Cs/(Cs+CP).
As may be seen from the above description, large variations in INPCM, cause correspondingly large variations in AMPCM, thereby affecting the normal operation of differential amplifier 260 and limiting its use to cases where the common-mode voltages in the input signal fall within a narrow range of values.
However, input signals can be received with a wide range of common mode voltages on path 101, for example, because the input signal may have been generated in an earlier circuit which is referenced to a different ground potential (in comparison with SHA 110). Alternatively, common noise component might have been added as common mode voltage on both terminals 290-1 and 290-2.
Various aspects of the present invention operate to increase the input common-mode range of a circuit (e.g., SHA 110) which accepts differential signals as inputs.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.